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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT356 8-input multiplexer/register; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state FEATURES * Non-transparent data latches * Transparent address latch * Easily expanding * Complementary outputs * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT356 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL 74HC/HCT356 (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT356 data selectors/multiplexers contain full on-chip binary decoding, to select one-of-eight data sources. The data select address is stored in transparent latches that are enabled by a LOW on the latch enable input LE. Data on the 8 input lines (D0 to D7) is clocked into a edge-triggered data register by a LOW-to-HIGH transition of the clock (CP). When the output enable input OE1 = HIGH, OE2 = HIGH or OE3 = LOW, the outputs go to the high impedance OFF-state. Operation of these output enable inputs does not affect the state of the latches and register. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay Sn, LE to Y, Y CP to Y, Y CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 24 20 3.5 123 25 22 3.5 125 ns ns pF pF HCT UNIT December 1990 2 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state PIN DESCRIPTION PIN NO. 8, 7, 6, 5, 4, 3, 2, 1 9 10 11 14, 13, 12 15, 16 17 18 19 20 SYMBOL D0 to D7 CP GND LE S0, S1, S2 OE1, OE2 OE3 Y Y VCC NAME AND FUNCTION data inputs 74HC/HCT356 clock input data (LOW-to-HIGH, edge-triggered) ground (0 V) address latch enable input (active LOW) select inputs output enable inputs (active LOW) output enable input (active HIGH) 3-state multiplexer output (active LOW) 3-state multiplexer output (active HIGH) positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state FUNCTION TABLE INPUTS ADDRESS (1) S2 X X X L L L L H H H H L L L L H H H H Notes X X X L L H H L L H H L L H H L L H H S1 X X X L H L H L H L H L H L H L H L H S0 CP X X X (2) (2) (2) (2) (2) (2) (2) (2) 74HC/HCT356 OUTPUTS OUTPUT ENABLE OE1 OE2 X H X L L L L L L L L L L L L L L L L X X L H H H H H H H H H H H H H H H H OE3 Y Z Z Z D0n D1n D2n D3n D4n D5n D6n D7n D0p D1p D2p D3p D4p D5p D6p D7p Y Z Z Z D0n D1n D2n D3n D4n D5n D6n D7n D0p D1p D2p D3p D4p D5p D6p D7p outputs in high impedance OFF-state DESCRIPTION H X X L L L L L L L L L L L L L L L L data is clocked into latch outputs do not change states 1. This column shows the input address set-up with LE = LOW (address latch is transparent). 2. CP is HIGH, LOW or . 3. D0n to D7n = data present at inputs D0 to D7 when the data latch clock made the transition from LOW-to-HIGH D0p to D7p = data previously latched into the data latch by the LOW-to-HIGH transition of the data latch clock H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH CP transition = HIGH-to-LOW CP transition Z = high impedance OFF-state December 1990 4 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state 74HC/HCT356 Fig.4 Functional diagram. December 1990 5 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state 74HC/HCT356 Fig.5 Logic diagram. December 1990 6 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER 74HC/HCT356 TEST CONDITIONS +25 -40 to +85 max. -40 to +125 min. max. 360 72 61 390 78 66 405 81 69 190 38 32 225 45 38 235 47 40 235 47 40 90 18 15 120 24 20 120 24 20 75 15 13 UNIT V WAVEFORMS CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 min. typ. max. min. tPHL/ tPLH propagation delay CP to Y, Y tPHL/ tPLH propagation delay Sn to Y, Y tPHL/ tPLH propagation delay LE to Y, Y tPZH/ tPZL 3-state output enable time OEn to Y, Y tPZH/ tPZL 3-state output enable time OE3 to Y, Y tPHZ/ tPLZ 3-state output disable time OEn to Y, Y tPHZ/ tPLZ 3-state output disable time OE3 to Y, Y tTHL/ tTLH output transition time 66 24 19 77 28 22 77 28 22 41 15 12 47 17 14 50 18 14 58 21 17 14 5 4 80 16 14 17 6 5 17 6 5 11 4 3 240 48 41 260 52 44 270 54 46 125 25 21 150 30 26 155 31 26 155 31 26 60 12 10 100 20 17 100 20 17 65 13 11 300 60 51 325 65 55 340 68 58 155 31 26 190 38 33 195 39 33 195 39 33 75 15 13 ns Fig.7 ns Fig.8 ns Fig.11 ns Fig.11 ns Fig.11 ns Fig.11 ns Figs 6, 7 and 8 tW clock pulse width CP HIGH or LOW ns Fig.6 tW latch enable pulse width LE 80 LOW 16 14 set-up time Dn to CP 50 10 9 ns Fig.8 tsu ns Fig.10 December 1990 7 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state Tamb (C) 74HC SYMBOL PARAMETER 74HC/HCT356 TEST CONDITIONS +25 -40 to +85 max. -40 to +125 min. 75 15 13 5 5 5 5 5 5 max. WAVEFORMS UNIT V CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.9 min. typ. max. min. tsu set-up time Sn to LE hold time Dn to CP hold time Sn to LE 50 10 9 5 5 5 5 5 5 14 5 4 -6 -2 -2 -8 -3 -2 65 13 11 5 5 5 5 5 5 th ns Fig.10 th ns Fig.9 December 1990 8 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types 74HC/HCT356 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT Dn, Sn OE3 LE OEn, CP UNIT LOAD COEFFICIENT 0.2 0.25 0.5 1.0 December 1990 9 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPZH/ tPZL tPZH/ tPZL tPHZ/ tPLZ tPHZ/ tPLZ tTHL/ tTLH tW tW tsu tsu th th propagation delay CP to Y, Y propagation delay Sn to Y, Y propagation delay LE to Y, Y 3-state output enable time OEn to Y, Y 3-state output enable time OE3 to Y, Y 3-state output disable time OEn to Y, Y 3-state output disable time OE3 to Y, Y output transition time clock pulse width CP HIGH or LOW latch enable pulse width LE LOW set-up time Dn to CP set-up time Sn to LE hold time Dn to CP hold time Sn to LE 16 16 10 10 5 5 26 28 29 17 18 17 20 5 8 6 4 5 0 -2 -40 to +85 -40 to +125 max. min. max. min. 51 59 63 34 34 33 33 12 20 20 13 13 5 5 64 74 79 43 43 41 41 15 24 24 15 15 5 5 max. 77 89 95 51 51 50 50 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74HC/HCT356 TEST CONDITIONS WAVEFORMS UNIT V CC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.7 Fig.8 Fig.11 Fig.11 Fig.11 Fig.11 Figs 6, 7 and 8 Fig.6 Fig.8 Fig.10 Fig.9 Fig.10 Fig.9 December 1990 10 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state AC WAVEFORMS 74HC/HCT356 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock (CP) to the output (Y, Y) propagation delays, the clock pulse width and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the select input (Sn) to output (Y, Y) propagation delays and the output transition times (LE = LOW). December 1990 11 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state 74HC/HCT356 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the address latch enable input (LE) pulse width, the latch enable input to output (Y, Y) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the set-up and hold times for the select input (Sn) to the address latch enable input (LE). December 1990 12 Philips Semiconductors Product specification 8-input multiplexer/register; 3-state 74HC/HCT356 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the set-up and hold times for the data input (Dn) to the clock (CP). (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing the 3-state enable and disable times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 13 |
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